[PDF.01ve] Flip-Flop Design in Nanometer CMOS: From High Speed to Low Energy

Flip-Flop Design in Nanometer CMOS: From High Speed to Low Energy

[PDF.sk09] Flip-Flop Design in Nanometer CMOS: From High Speed to Low Energy

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 | #4666653 in Books |  2014-10-15 | Original language:English | PDF # 1 |  9.21 x.69 x6.14l,.0 | File type: PDF | 260 pages

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||From the Back Cover||This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according

This book provides a unified treatment of Flip-Flop design and selection in nanometer CMOS VLSI systems. The design aspects related to the energy-delay tradeoff in Flip-Flops are discussed, including their energy-optimal selection according to the targeted application, and the detailed circuit design in nanometer CMOS VLSI systems. Design strategies are derived in a coherent framework that includes explicitly nanometer effects, including leakage, layout parasitics and...

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