[PDF.44th] Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

[PDF.sp42] Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

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 | #1424715 in Books |  2013-11-16 | Original language:English | PDF # 1 |  9.20 x.80 x6.00l,1.45 | File type: PDF | 245 pages

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||From the Back Cover||This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects.  The authors identify the key challenges facing 3D IC tes

This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimizati...

You can specify the type of files you want, for your device.Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs   |  Brandon Noia, Krishnendu Chakrabarty. I have read it a couple of times and even shared with my family members. Really good. Couldnt put it down.

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